Aim of the experiment :-
To Design a Half Adder using Data Flow Modelling In verilog Code And show results in testbench form.
Theory :
It is a combinational circuit with two binary inputs and outputs. Its adds the input and produces the corresponding sum and carry bits . its is an arithmetic circuit used to perform arithmetic operation of addition of two single bit words .
Here,
The Sum bit and Carry bit , acccording to the rules of binary addition are given by :
The sum (s) is the Xor of A and B ( It Represents the LSB of the sum).The Carry (C) is the and
Of the A and B ( It Is 0 unless both the inputs are 1). Therefore C = A.B
A Half Adder can therefore be realized by using one X-OR gate and one And Gate .
A Half Adder Can also be realized in universal logic by using either only NAND Gates or Only NOR Gates .
In Data flow modelling instead of using ' XOR ' ' AND ' Commands in the module we use
Operators assigned to those logic gates .
Verilog Code :-
module halfadder( s,c,a,b);
output s;
output c;
input a;
input b;
assign s = a^b ;
assign c= a&b;
endmodule
Conclusion :-
The Half Adder Circuit was designed and simulated using Xilinx Verilog Software.
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Posted at 23:28 | by
Sudhir Ufaniya
